In modem integrated circuit design, a high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device is widely used. A voltage endurance of the LDMOS FET is achieved through a drift region of the drain of the MOS FET and a principle of reduced surface field (RESURF). The drift region is formed by performing an ion implantation process and a high temperature thermal diffusion process. The drift region usually includes a thermal oxide layer with a certain thickness, a polysilicon is laminated on the thermal oxide layer, an upper surface potential distribution on the drift region is changed to realize a full depletion of the drift region, an extreme voltage endurance under a limited drift region length is achieved.
Generally, a high voltage process for a line width greater than 0.35 μm employs a local oxidation of silicon (LOCOS) method to isolate, a stacked field oxide used by the oxide layer on the drift region is a LOCOS method. A field oxide region is defined by photolithography, and a field oxide of a first step is grown. A photolithography process is performed to define a drift region, a thermal oxidation layer is performed to grow an oxide layer of the drift region, meanwhile a second step of growth is achieved through overlapping growth on the field oxide region. Thicknesses of the drift region thermal oxidation layer and the field oxide can be fitted in any combination, a better depletion of the drift region can be achieved, a length of the bird beak of the field oxide cannot be controlled, an area of the source region can be affected, which will lead to an electric leakage when in a serious situation, causing a yield thereof to be low.